This invention relates to a phase comparator applied to a clock data recovery (CDR) circuit which mainly is integrated in a digital large scale integration (LSI) circuit and which is used in purposes necessary to operate at a high speed.
The phase comparators applied to the CDR circuit of the type described are composed of all of digital logic to be adapted to binary result outputs. Such types of the phase comparators are mostly adopted which are exemplified by ISSCC 2001 J. Savoi, B. Razavi, or the like. The phase comparators of the type described are generally called a bang-bang type in the art. The phase comparator of the bang-bang type is characterized in that it has a large gain and a large noise-resistance and it is easy to design to operate at a high-speed.
In the manner which will later be described in conjunction with FIG. 1, a conventional phase comparator of the type described comprises a flip-flop circuit consisting of first through third D-type flip-flops. The flip-flop circuit is supplied with an input data signal having a digital signal format and an input clock signal for use in data extraction. The input data signal is a received data signal. The first through the third D-type flip-flops are called first through third latch circuits, respectively. Each of the first through the third latch circuits has a data input terminal, a clock input terminal, and a data output terminal. The first latch circuit carries out a latch operation in synchronism with a trailing edge of a signal supplied to the clock input terminal thereof while each of the second and the third latch circuit carries out a latch operation in synchronism with a leading edge of a signal supplied to the clock terminal thereof.
The first latch circuit has a first data input terminal supplied with the input data signal and a first clock input terminal supplied with the input clock signal. The first latch circuit latches the input data signal in synchronism with a trailing edge of the input clock signal to produce a first latched signal from a first data output terminal thereof. The second latch circuit has a second data input terminal supplied with the input data signal and a second clock input terminal supplied with the input clock signal. The second latch circuit latches the input data signal in synchronism with a leading edge of the input clock signal to produce, as an output data signal, a second latched signal from a second data output terminal thereof. The third latch circuit has a third data input terminal supplied with the first latched signal and a third clock input terminal supplied with the second latched signal (or the output data signal). The third latch circuit latches the first latched signal in synchronism with a leading edge of the second latched signal (or the output data signal) to produce, as an output up/down signal, a third latched signal from a third data output terminal thereof.
That is, the conventional phase comparator of the type described compares a phase of the leading edge of the input data signal with a phase of the trailing edge of the input clock signal to produce the output up/down signal indicative of a phase difference between the input data signal and the input clock signal. In other words, the output up/down signal indicates one of lag and lead phases which the input clock signal has in comparison with the input data signal. When the input clock signal has the lag phase in comparison with the input data signal, the conventional phase comparator produces, as the output up/down signal, a signal having a logic “1” level indicative of an “up” state. When the input clock signal has the lead phase in comparison with the input data signal, the conventional phase comparator produces, as the output up/down signal, a signal having a logic “0” level indicative of a “down” state.
Inasmuch as the conventional phase comparator has structure where only one of phase difference related to the leading edge of the input data signal is reflected to a comparison result, it results in decreasing a phase margin on carrying out a clock recovery and it is difficult to obtain a sufficient noise-resistance for jitter variation, in the manner which will later be described in conjunction with FIGS. 5A through 5D.
Various other phase comparators of the type are already known. By way of example, a digital PLL (phase-locked loop) circuit is disclosed in U.S. Pat. No. 6,236,696 issued to Yasushi Aoki et al. According to Aoki et al, the digital PLL circuit includes a phase comparing section composed of N phase comparators each of which comprises a flip-flop circuit. The flop-flop circuit has a data input terminal supplied with a sampled data and a clock input terminal supplied with a selected clock signal.
Japanese Unexamined Patent Publication of Tokkai No. 2000-68,991 or JP-A 2000-68991 discloses a clock recovery circuit which attains identification and regeneration of clock data without requirement of a high speed circuit. According to JP-A 2000-68991, the clock recovery circuit includes a phase comparator for detecting a phase difference between an input signal and a voltage controlled signal (a clock signal) supplied from a VCO (voltage controlled oscillator). The phase comparator comprises first and second D-type flip-flops, first and second AND gates, a delay circuit, and an adder. The first D-type flip-flop latches a data signal in synchronism with the clock signal to produce a first non-inverted latched signal and a first inverted latched signal. The first AND gate ANDs the data signal and the first inverted latched signal to produce a first ANDed signal. The second D-type flip-flop latches the first non-inverted latched signal in synchronism with an inverted clock signal to produce a second non-inverted latched signal and a second inverted latched signal. The second non-inverted latched signal is produced as a data output signal. The delay circuit delays the second inverted latched signal to produce a delayed signal. The second AND gate ANDs the first non-inverted latched signal and the delayed signal to produce a second ANDed signal. The adder adds the first ANDed rate, by using the AND gates, a phase difference detection is carried out only at leading edge or trailing edge of the clock signal.
An error-suppressing phase comparator is disclosed in U.S. Pat. No. 6,249,188 issued to Yoshiaki Kaneko. According to Kaneko, the error-suppressing phase comparator includes a phase comparator. When an edge of a recovered clock signal leads an edge of a data signal, the phase comparator produces a pulse of a down signal in order to delay the lead. When the edge of the recovered clock signal lags the edge of the data signal, the phase comparator produces a pulse of an up signal in order to advance the lag. At any rate, the phase comparator generates the pulse of the up signal or the down signal depending on lead or lag of a trailing edge of the recovered clock signal.